The present invention relates to automatic test equipment for the production testing of large digital circuit modules.
Recent advances in digital circuit technology have led to the widespread manufacture and use of "motherboard" circuit modules typically containing approximately 150 integrated circuit (IC) chips mounted to dual-in-line packages contained on large printed circuit boards typically of approximately 200 square inches. Because of their large size and complexity, and because of the absence of test points or connector pins communicating with circuits that may be several logic levels away from either a module input or module output pin, it is only with extreme difficulty and at considerable expense in time and money that a board of this kind may be tested and a fault diagnosed down to a particular defective IC during production testing without the use of various diagnostic aids that have been developed in the industry.
The problems of testing large and complex logic circuits may be separated into two categories, those involving the testing of combinational logic systems and those involving the testing of sequential logic systems.
A combinational logic system is defined as one that consists entirely of gates (AND, OR, NAND, NOR, and Exclusive OR). In a combinational logic system no clock is required and after the inputs have been established, and disregarding settling time, the outputs are immediately available. For small circuit modules it is appropriate for a test programmer, after studying the schematics of the circuit module, to create test patterns and to write test programs so that automatic test equipment, under control of a computer executing these programs, can apply these test patterns to the circuit module, monitor one or several output pins, determine if the test failed, and write out a repair order on a suitable computer printer if the test failed. These test programs were written to exercise one gate or one flip-flop at a time or to completely test one gate or one flip-flop before using it to supply an input to a second gate or flip-flop to be tested, so that whenever a failure occurred, it would be immediately obvious which circuit had failed and the repair order could be printed immediately. Upon the detection of a fault, the test program would terminate, the particular gate or flip-flop would be repaired, and the board would be reinserted into the test equipment for retest. When all faults were repaired the test program would be completely executed with no faults detected. With the advent of large circuit modules of the kind specified above, this simple test system could no longer be used for several reasons.
In a large digital circuit module with approximately 150 IC's, it has been calculated that approximately 9,000 test patterns would be required to fully test such a system and diagnose a fault down to an IC if a fault were detected. This work could not be done by a test programmer for two reasons. First, the time it would take for a test programmer to generate that many patterns and produce a program to execute those patterns and to diagnose any combination of faults down to an IC whose failure would produce that particular combination of faults would require an excessive amount of time and therefore, would involve a large expense in the production of the circuit board. Using this kind of system a circuit board could not be produced at a competitive cost. Furthermore, because of the tediousness of the work and the complexity of the circuit, the patterns thus generated would contain errors which would detract immediately from the usefulness of the program in that one would never know whether the board was being fully tested, and would result in a large amount of follow-up corrective work on the programs in inventory.
More recently, computers have been used to automatically generate test bit patterns for testing and diagnostic purposes. First, the entire circuit must be coded in a form that is recognizable by the computer. This can be done by reducing all of the digital circuits on the board to their logic equation form. This information may already be available to the test programmer on a data base originally generated for the simulation of a digital circuit or for automatic pin listing, back plane wiring, or circuit board etching equipment. A computer can then, using one of several algorithms developed for the purpose, analyze the digital circuit, node by node, and determine a unique logical path from the module input pins to a module output pin that will test each particular point or node of the logical circuit, determine what input bit pattern must be applied to all other input pins to block off the interaction from all other logic circuits on the module, determine what input bits are required to test that particular circuit node, and determine on which particular module pin the output may be tested.
A test of this kind could be applied to every node on the entire logic module. However, if peripheral circuits on the module must be set up in a non-interfering state in order to test a particular node and if a fault in one of these peripheral circuits will result in a test failure, then each test must of necessity test more than one circuit node. A program written to take advantage of this characteristic may be used to make a large reduction in the number of tests necessary to completely test and diagnose one circuit module. A method of computing the minimum set of patterns required to test a combinational logic system, and including a method of generating the patterns for testing such a system, is described in "A Method To Compute A Set Of Fault Detection Tests For Combinational Nets" by Virendra K. Kadakia, published in June, 1967 by the Polytechnic Institute of Brooklyn.
The next major problem to be overcome in the generation of test patterns according to the system described above is that in actual circuits one rarely finds a pure combinational net. Because sequential circuits, usually in the form of flip-flops, are almost always interspersed through the circuits making the testing of these circuits impossible by standard combinational net methods. That is to say, to test such a mixed logic system one must not only need to know the input bit pattern but also the states of the sequential logic elements, and furthermore, must provide clock pulses and known how many clock pulses have been received by these sequential logic elements before the output has been inspected.
One method of testing a circuit module containing a mixture of combinational and sequential elements is to redesign the module by adding enough additional circuitry so that all of the sequential elements, upon the receipt of a suitable test signal at a module input pin, may be connected together as one large shift register. This usually does not require substantial additional circuitry since, for most ordinary uses, the standard integrated circuit shift register may be loaded either in parallel or through a shifting operation so that this standard shift register in its serial mode may be used as the shift register and in its parallel mode may be used as a collection of individual flip-flops by the circuit. In this case, the only additional logic that would normally be required would be multiplexors for passing data into and out of these shift registers and a control line to control the integrated circuit into either its parallel or serial mode of operation. Also, two connector pins would have to be added to the module, one for the control line input and one for the data input/output.
Using this shift register technique in the testing of sequential and combinational elements on a circuit module, the test process would be as follows. Generally, the flip-flops on the module would be tested first. If they pass the test successfully then they will be considered an extension of the test station and used to test the remaining combinational logic. Specifically, to initially test the sequential elements, all of the flip-flops on the module are connected in shift register configuration by an appropriate signal on the control line, and then serially loaded with a test pattern. This test pattern is then serially unloaded back out to the test station. With the operation of the shift register elements thus verified, the flip-flops may now be used as test points on the module. A test pattern is now applied to a particular combinational net. This pattern is either applied to the module connector pins or is shifted into the shift register. The control line then reconnects the sequential elements into their original flip-flop circuit functions, and after settling time, the network output signal appears either at a module output pin or at the input to a flip-flop. If the output bit is available at a module connector pin it is simply passed along to the test station for analysis. If the bit is available as an input to a flip-flop, a clock is issued to the module, clocking the bit into the flip-flop. All flip-flops on the module are then reorganized into a shift register and the data bit is shifted out serially to the test station. This technique not only allows for the automatic testing of circuit modules with intermixed sequential and combinational elements, but also, in effect, provides for a multiplicity of test points scattered through the internal logic of the module in that any flip-flop may be used as either an input or an output test point.
The technique of testing sequential elements initially by interconnecting them as a shift register and then using these same sequential elements as additional input and output test points to test the remaining combinational logic is described in an article by Michael J. Y. Williams entitled, "Enhancing Testability of Large Scale Integrated Circuits Via Test Points and a Additional Logic" published by Stanford University, September, 1970.
Given a module containing built-in diagnostic shift registers as described above, and assuming the automatic generation of the required nine thousand sets of bit patterns per module necessary for complete fault detection and diagnosis wherein each bit pattern may range over 100 bits, there remains a need for a test system that will exercise the module according to these pre-calculated bit patterns, test the module and diagnose any problem found down to a replaceable unit. Furthermore, this system must be suitable for operation by relatively untrained factory personnel and operate at speeds to allow for economical production testing.